We have proposed and demonstrated a device fabrication process of physically defined quantum dots utilizing electron beam lithography employing a negative-tone resist toward high-density integration of silicon quantum bits (qubits). The electrical characterization at 3.8K exhibited so-called Coulomb diamonds, which indicates successful device operation as single-electron transistors. The proposed device fabrication process will be useful due to its high compatibility with the large-scale integration process.

To improve throughput of Electron Beam Direct Writing (EBDW) with Character Projection (CP) method, a structured routing architecture (SRA) has been proposed to restrict VIA placement and wire-track transition. It reduces possible layout patterns in the interconnect layers, and increases VIA and metal figure numbers in the EB shots while suppressing the CP character number explosion. In this paper, we discuss details of the SRA design methodology, and demonstrate the CP performance by SRA in comparison with other EBDW techniques. Our experimental results show viable CP performance for practical use, and prove SRA's feasibility in 14nm mass fabrication.

Character projection (CP) is a high-speed mask-less exposure technique for electron-beam direct writing (EBDW). In CP exposure of VIA layers, higher throughput is realized if more VIAs are exposed in each EB shot, but it will result in huge number of VIA characters to cover arbitrary VIA arrangements. We adopt one-dimensional VIA arrays as the basic CP character architecture to increase VIA numbers in an EB shot while saving the stencil area by superposed character arrangement. In addition, CP throughput is further improved by layout constraints on the VIA placement in the detail routing phase. Our experimental results proved the feasibility of our exposure strategy in the practical CP use in 14nm lithography.

We investigated optical transmission characteristics of aluminum thin films with periodic hole arrays in sub-wavelength. We divided white light into several color spectra using a color filter based on the surface plasmon resonance (SPR) utilizing aluminum showing high plasma frequency. By optimizing a hole-array period, hole shape, polarization and index difference of two surface, transmittance of 30% and full-width at half-maximum of around 100 nm were achieved.

Organic static induction transistor (OSIT) is a promising driving device for the displays, since it shows high-speed, high-power and low-voltage operation. In this study, the OSIT with fine gate electrode patterned by electron beam exposure were fabricated. We investigated the basic electrical characteristics of copper phthalocyanine OSIT and compared with the calculation results obtained by two-dimensional (2D) device simulator. The experimental results show that the gate modulation improved by reducing the electrode gap and on/off current ratio depends on the gate gap.

A method for measuring the luminance distribution of an electron beam spot was described, which is fundamental to evaluate the resolution of a color display tube. First, to achieve high sensitivity and wide dynamic range identical to those of visual inspection, we proposed the use of an ICCD camera for imaging and two levels of sensitivity. With that method, we were able to measure the luminance distribution of an electron beam spot over a range of currents that extends from the extremely weak cathode current region to large current that correspond to the peak luminance. Specifically, we were able to measure the entire distribution shape from the base to the peak for beam spots in the cathode current range from 20 µA to 300 µA, while compensating the absolute luminance level. Second, a reconstruction algorithm of entire beam distribution from the shape of the masked part of the beam was also proposed, in which shift error is compensated to reduce the variance in measurement results caused by jitter noise in the conventional image processing method. That algorithm improves the reproducibility of repeated measurements. Specifically, a function for estimating the actual shift from the first-order moment of the image was incorporated into the spot shape reconstruction algorithm, resulting in a reduction of the standard deviation for repeated measurements of the horizontal beam spot diameter at 5% intensity from 0.02 mm to 0.005 mm.

We propose a shot reduction technique of character projection (CP) Electron Beam Direct Writing (EBDW) using combined cell stencil (CCS) or the advanced process technology. CP EBDW is expected both to reduce mask costs and to realize quick turn around time. One of major issue of the conventional CP EBDW, however, is a throughput of lithography. The throughput is determined by numbers of shots, which are proportional to numbers of cell instances in LSIs. The conventional shot reduction techniques focus on optimization of cell stencil extraction, without any modifications on designed LSI mask patterns. The proposed technique employs the proposed combined cell stencil, with proposed modified design flow, for further shot reduction. We demonstrate 22.4% shot reduction within 4.3% area increase for a microprocessor and 28.6% shot reduction for IWLS benchmarks compared with the conventional technique.

The feasibility of a new transistor structure was demonstrated through an experimental observation of current gain and voltage gain. The proposed transistor structure is a hot electron transistor without a base layer to minimize scattering. Electron emission from the emitter is controlled using positively biased Schottky gate electrodes located on both sides of the emitter mesa. Monte Carlo simulation shows an estimated delay time of 0.17 ps and low gate leakage current with open-circuit voltage gain over unity. To confirm the basic operation, the device with a 25 nm wide emitter was fabricated. To obtain saturated current-voltage characteristics, the emitter was surrounded by gates and parasitic regions were eliminated by electron beam lithography. The observed open-circuit voltage gain was 25. To obtain a low leakage current, an electron energy smaller than the Γ-L separation was necessary to maintain the ballistic nature of the electron. When the gate-emitter voltage was 0.8 V, the gate leakage current was only 4% of the collector current. Thus voltage amplication and current amplification were confirmed simultaneously.

We propose a cell library development methodology for throughput enhancement of character projection equipment. First, an ILP (Integer Linear Programming)-based cell selection is proposed for the equipment for which both of the CP (Character Projection) and VSB (Variable Shaped Beam) methods are available, in order to minimize the number of electron beam (EB) shots, that is, time to fabricate chips. Secondly, the influence of cell directions on area and delay time of chips is examined. The examination helps to reduce the number of EB shots with a little deterioration of area and delay time because unnecessary directions of cells can be removed. Finally, a case study is shown in which the numbers of EB shots are shown for several cases.

A Cyclotron Wave Converter, having decreased magnetic intensity is discussed. Two microwave cavities with uniform and quadruple (or six-pole) electric field in the gap of interaction are used to transform microwave power into the kinetic power of the electron beam fast cyclotron wave. As a result of it, magnetic flux density occurs in two (or three) times lower. The latter is very important to create a compact, powerful and efficient microwave/DC power converters operating at different frequencies including short centimetric and long millimetric wavebands.

Reducing moire is an important consideration in CRT design. This paper aims to investigate how the visibility of the inverse-phase raster moire, a typical pattern of the raster moire, is influenced by the distribution of the electron beam and the structure of shadow mask apertures. First, a simple model based on the luminance distribution on the CRT screen and characteristics of the human vision was used to calculate the perceived intensity of the inverse-phase raster moire. This calculation was made to examine the effect of model parameters. It showed that the inverse-phase raster moire consists of (1,1)-order moire components. It was also found that the perceived intensity increases with a decrease in electron beam diameter and with an increase in horizontal aperture pitch. In addition, a subjective evaluation test was conducted using an inverse-phase moire pattern reproduced by the image simulation. Test results agreed with the calculated results. Finally, it was revealed that when an electron beam shape having a Gauss distribution was used, most of the raster moire is the inverse-phase raster moire caused by the (1,1)-order component, while the (2,2)-order moire component was very low.

Gd2O2S:Tb phosphor thin films have been prepared using the simple technique of electron beam evaporation for large area display applications. The photoluminescence and excitation spectra measurement of Gd2O2S:Tb phosphor thin films suggest that Tb3+ is incorporated into the Gd2O2S lattice at gadolinium sites. Relatively efficient electroluminescence is observed from a ZnS/Gd2O2S:Tb/ZnS sandwich cell.

We investigate the basic properties of focused electron beam (FEB)-damaged Josephson junctions on silicon (Si) substrates for high-frequency device applications. YBa2Cu3O7-y (YBCO) Josephson junction arrays were also fabricated by FEB irradiation to confirm the junction uniformity and to investigate their applicability. The junctions exhibit resistively shunted junction (RSJ)-like current-voltage (I-V) curves and the microwave-induced Shapiro steps for all operation temperatures. Two-junction arrays show single-junction-like behavior with the Shapiro steps in an array up to 2 mV. Microwave-induced Shapiro steps correspond to the double voltages Vn=2nVJ, where VJ=f0h/2e in two-junction arrays. The microwave power dependence of I-V curves shows the steps corresponding to the RSJ model.

A novel method for the guided-probe diagnosis of high-performance LSIs containing macrocells, which have no internal netlist essential to the diagnosis, has been developed. In this method, the macrocell netlist is derived from its layout by extracting a leaf-cell-level netlist and is combined with the original one. Logic models for the leaf cells in the extracted netlist are also generated to obtain the logic-simulation data in the macrocells. The logic modeling is extended for application to memory macrocells, based on the idea that analog-behavior leaf cells in the memory macrocells are converted into logically equivalent circuits for logic simulation. Specifically, sense amplifiers and wired-or connections on bit lines are replaced with the corresponding logic-behavior models. The proposed method has been successfully applied to actual design data of LSIs containing macrocells, and it has been verified that it enables fault paths inside macrocells to be accurately traced and that the logic models give good timing resolution in the logic simulation. Using the proposed method, LSIs containing macrocells will be able to be diagnosed regardless of the macrocell types, without the need for a "golden" device, by an electron-beam guided probe system.

The high resolution CRT displays used for computer monitor and high performance TV often produce a pattern of bright and dark stripes on the screen called a moire pattern. The elimination of the moire is an important consideration in the CRT design. In this paper, we propose a method for evaluating a moire pattern based on the measurement data of the electron beam distribution. (1) We describe a mathematical expression of the process whereby a moire pattern is produced. By applying the electron beam measurement data into the formulae, precise value of the period and the contrast of a moire are calculated from the actual data of the electron beam profile and the distribution of apertures of the shadow mask. (2) The visibility of the moire is evaluated by plotting the calculation results on the contrastperiod plane, which consists of visible and invisible moire pattern regions based on experimental results of the psychological tests. (3) In addition to the analysis by calculation, the visibility of moire patterns can be visually examined by simulating moire patterns using the same data as above calculation. Since not only fundamental design parameters such as a shadow mask pitch and a scanning line pitch but also details of an electron beam profile such as a distortion or an asymmetry can be examined, a newly developed method contributes the efficiency of the CRT design.

A hierarchical fault tracing method for VLSIs with bi-directional busses from CAD layout data in the CAD-linked electron beam test system is described. When fault tracing reaches at a cell connected to a bi-directional bus, our method is able to judge the direction of the signal flow, input or output, by using waveforms acquired by an EB tester, in a consistent manner independently of circuit functions as with a previously proposed tracing method for circuits without bi-directional busses.

We studied effects of 50-200-keV electrons on semiconductor devices using BEASTLI (backscattered electron assisting LSI inspection) method. When irradiating semiconduc-tor devices with such high-energy electrons, we have to note two phenomena. The first is surface charging and the second is device damage. In our study of surface charging, we found that a net positive charge was formed on the device surface. The positive surface charges do not cause serious influence for observation so that we can inspect wafers without problems. The positive surface charging may be brought about because most incident electrons penetrate the device layer and reach the conducting substrate of the semiconductor device. For the device damage, we studied MOS devices which were sensitive to electron-beam irradiation. By applying a 400- annealing to electron-beam irradiated MOS devices, we could restore the initial characteris-tics of MOS devices. However, in order to recover hot-carrier degradation due to neutral traps, we had to apply a 900- annealing to the electron-beam irradiated MOS devices. Thus, BEASTLI could be successfully used by providing an apporopri-ate annealing to the electron-beam irradiated MOS devices.

An automatic transistor-level performance fault tracing method is proposed which is applicable to the case where only CAD layout data is available in the CAD-linked electron beam test system. The technique uses an integrated algorithm that combines a previously proposed transistor-level fault tracing algorithm and a successive circuit extraction from CAD layout data. An expansion of the algorithm to the fault tracing in a combined focused ion beam and electron beam test system which enables us to measure signals on the interconnections in the lower layers is also described. An application of the technique to a CMOS model layout with about 100 transistors shows its validity.

A Monte Carlo method for the passage of electrons based on a single scattering model is developed. A code based on this method is operable on personal computers, and has been applied to analyze electron behavior in a layered system consisting of Ti (an accelerator window), air, cellulose triacetate (CTA) and backing material irradiated by 300 keV electrons. The energy spectra and the angular distributions of electrons on the CTA surface as well as depth distributions of energy deposition in the CTA for various backing materials have been obtained. Some of these results are compared with experiments, and show fairly good agreement.

Precise matching of the SEM (secondary electron microscope) image of the DUT (device under test) interconnection pattern with the CAD layout is required in the CAD-linked electron beam test system. We propose the point pattern matching method that utilizes a corner pattern in the CAD layout. In the method, a corner pattern which consists of a small number of pixels is derived by taking into account the design rules of VLSIs. By using the corner pattern as a template, the matching points of the template are sought in both the SEM image and CAD layout. Then, the point image obtained from the SEM image of DUT is matched with that from the CAD layout. Even if the number of points obtained in the DUT pattern is different from that in the CAD layout due to the influence of noise present in the SEM image of the DUT pattern, the point matching method would be successful. The method is applied to nonpassivated and passivated LSIs. Even for the passivated LSI where the contrast in the SEM image is mainly determined by voltage contrast, matching is successful. The computing time of the proposed method is found to be shortened by a factor of 4 to 10 compared with that in a conventional correlation coefficient method.